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Course Content
MODULE 1
0/10
INTRODUCTION
01:37
1 Explain about Evolution of Computer-Aided Digital Design (CAD)?
05:45
2 What are Emergence of Hardware Description Languages (HDLs)?
04:14
3 Explain about typical design flow ? and explain about importance of HDL?
06:53
4 Explain about popularity of Verilog HDL and trends in HDL?
04:39
5 Explain about design methodologies , top- down and bottom-up design methodologies?
06:05
6 Explain about Module?
03:17
7 Explain about component of simulation?
03:56
8 Explain about Design Block(Test Bench) with example?
02:52
9 Explain about Stimulus Block (Test Bench) with example?
02:55
MODULE 2
0/11
1 Explain about Lexical conventions in verilog HDL?
04:49
2.Explain about Data types in verilog?
05:16
3 Explain about system tasks in Verilog HDL?
08:26
4 Explain about Compiler directives?
04:59
5 Write a symbol for basic memory component and explain its parts? And explain about multiport memories?
08:26
6 Compute the 12-bit ECC word corresponding to the 8-bit data word “01100001”
16:10
7 Design a 64K*16 bit composite memory using 16k*8 bit component?
02:20
8 Write difference between Asynchronous static ram and synchronous static Ram?
02:07
9 Using a hamming code , how many check bits are required for single error correction and double error detection for 4-bit data word?
03:10
10 Determine wheather there is an error in the ECC word 000111000100 and if so correct it?
05:18
11 Develop a Verilog model of a dual-port, 4K _ 16-bit flow through SSRAM. One port allows data to be written and read, while the other port only allows data to be read.
03:03
MODULE 3
0/9
1.Outline and explain the internal organisation of FPGA?
10:53
2.Briefly explain programmable array logic ?
05:25
3.Explain the concept of differential signalling ? how does differential signalling improves noise immunity?
04:31
4.What distinguishes a platform of FPGA from a simple FPGA?
03:46
5.Explain different types of PCB design?
05:12
6.Explain internal organisation of CPLD,with neat diagram?
04:23
7.Explain different types of packaging and circuit boards?
03:48
8.Define signal integrity? Discuss ground bounce issue in signal integrity and technique is used to reduce ground bounce effect?
04:37
9.What are purpose of logic blocks and I/o blocks in FPGA?
03:22
MODULE 4
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1.Explain with a neat diagram , for R/2R ladder DAC?
05:47
2.Explain with a neat diagram , for R-string DAC ?
05:20
3.Explain any four serial interface standards?
10:50
4.Explain any four analog sensors?
06:27
5.Explain flash ADC with the help of necessary diagram?
06:21
6.Explain Successive approximation ADC with the help of necessary diagram?
05:16
7.Disucuss about multiplexed buses ?
05:34
8.Explain about tristate buses and Weak drive?
03:22
9.Explain about blocking and Non-blocking statements?
03:40
10.Explain the following I/o synchronization techniques
03:09
MODULE 5
0/8
1.Explain briefly area,power and timing optimization in digital circuits?
05:42
2.Explain fault model and fault simulation?
06:48
3.Demonstrate Built-In Self Test (BIST) techniques?
06:20
4.Explain floor plan, placement and routing of ASIC physical design.
07:02
5.Explain the concepts of scan design and boundary scan?
07:09
6.Briefly describe techniques used in power optimization?
05:46
7.What is the distinction between logical partition and physical partition ?
03:55
8.Difference between tasks , functions , declaration and Invocation with examples?
04:15
DIGITAL SYSTEM DESIGN USING VERILOG || ECE stream || Very Important Questions Explained with Concepts || All 5 modules || BEC654A || Last moment exam preparation
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