Limited time offer! Use '15OFFLH' to get a discount of 15% on all your purchases!
Course Content
MODULE 1
0/7
1.Explain the operation of MOSFET with necessary diagrams.Also derive the eq for drain current in linear and saturation region of operation
14:26
2.Draw the circuit of CMOS inverter and explain its DC transfer characteristics
12:51
3,Explain the following non-ideal effects channels length modulation ,mobility degradtion
06:42
4.Implement a D flipflop using transmission gate and explain its operation with necessary timing diagram
08:39
5.Implementation of a 4:1 multiplexer & 2:1 MUX using transmission gate
09:27
6.With necessary circuit diagram explain the operation of tristate inverter.Also realize 2:1 MUX using tristate inverter
09:08
7.Realize CMOS compound gate for function
09:33
MODULE 2
0/6
Q.1 Explain various steps in CMOS n-well process with necessary diagrams.
13:52
Q.2 With neat diagrams, explain the lambda design rules for wires, contact cuts, Transistors and for two metal layers.
09:30
Q.3 Explain layout rules for transistors.
06:41
Q.4 Define scaling. Explain constant field scaling and constant voltage scaling and why constant voltage scaling is usually preferred over full scaling.
20:36
Q.5 Mention different types of MOSFET capacitances with necessary diagrams and equations. Capacitance in cut off, linear and saturation region.
20:03
Q 6.Draw the stick diagram for boolean function
09:04
MODULE 3
0/8
Q1. Develop RC delay model to compute the delay of the logic circuit and calculate the delay of the unit sized inverter driving another unit inverter.
07:43
Q2. Construct necessary equivalent circuits using RC delay model to compute the propagation delay of 3-input NAND gate with transistors width chosen to achieve effective rise and fall resistance equal to that of a unit inverter.
09:14
Q3. Estimate the propagation delay for unit inverter driving ‘m’ identical unit inverters using Elmore delay.
11:02
Q4.problem
14:00
Q5.if a unit transistor
03:50
Q6. Explain linear delay model
16:22
Q6A. Explain: 1) pseudo nMOS 2) ganged CMOS 3) skewed gates 4) CVSL with necessary circuit examples.
28:16
Q7.Explain the various stage of planning
15:25
MODULE 4
0/7
Q1. Explain resettable latches and flipflops using CMOS transmission gate.
15:30
Q2. Explain dynamic logic.
11:52
Q3. Explain pulsed latches with schematic and waveforms.
10:20
Q4. Explain domino logic.
07:21
Q5. Draw and explain the features of C2MOS latch.
11:46
Q6. With neat circuit diagrams, explain 4 transparent latches. Write the advantage and disadvantage of each.
14:31
Q7.problem
09:10
MODULE 5
0/6
Q.1 With neat schematic diagram explain the operation of full CMOS static RAM cell.
12:47
Q.2 With neat schematic diagram explain the operation of three transistor DRAM cell.
04:52
Q3. What is static RAM? With neat diagram explain any 3 static RAM circuit.
12:26
Q4. Draw the diagram of 4bit * 4bit NOR based ROM array, explain the functioning.
11:40
Q.5 Explain the different fault models.
14:12
Q6. Write short notes on: 1) Built in Self Test 2) Scan Design
12:54
VLSI DESIGN AND TESTING || ECE stream || Very Important Questions Explained with Concepts || All 5 modules || BEC602|| Last moment exam preparation
Previous
Next
0% Complete

Want to earn money while learning? check out our refer and earn program

click here

Follow us on social media for regular updates

Whatsapp Instagram Linkedin Youtube

Quick Links

"At LearnyHive, we help students with the essential last-minute preparation they need to clear their semester exams and provide tutors with the platform they deserve."
"At LearnyHive, we help students with the essential last-minute preparation they need to clear their semester exams and provide tutors with the platform they deserve."
Amar Karthik Co-Founder & CTO

Tutorials

Whatsapp Instagram Linkedin Youtube
Copyright © LearnyHive.com 2025. All rights reserved.
Designed, Developed and Maintained by UnikBrushes.
Terms, Privacy Policy, Cookies Policy, Refund Policy